This invention relates to electronic devices comprising a thin-film transistor and methods of manufacturing such. The device may be a flat panel display, for example, an active-matrix liquid-crystal display, or another type of large-area electronic device, for example, a large-area image sensor or touch sensor, or a thin-film data store or memory device.
There is currently much interest in developing thin-film circuits with thin-film transistors (hereinafter termed "TFTs") on glass and on other inexpensive insulating substrates for large-area electronics applications. Such TFTs may form the switching elements in a cell matrix, for example in a flat panel display as described in U.S. Pat. No. 5,130,829, and/or in integrated drive circuits for such cell matrices.
In the development and manufacture of large-area electronic devices, it is recognised that the performance of the TFTs can depend critically on the quality of the electrical contact between the source and drain electrodes and the semiconductor layer providing the channel region. There is a need to be able to form good quality contacts reproducibly and hence uniformly. A variety of materials are known for the electrodes and semiconductor layers. The semiconductor layer is usually of silicon in an amorphous or microcrystalline or polycrystalline form. The silicon-based regions may be contacted by electrodes of, for example, chromium, molybdenum, aluminium, and indium tin oxide (ITO). These electrodes may themselves be contacted by a conductive film which forms a pattern of interconnection tracks between these circuit elements. In most situations it is desirable for the electrode to make an ohmic contact of low resistance with the semiconductor.
One particular form of TFT is the so-called top-gate staggered TFT in which the source and drain electrodes are provided underneath an amorphous silicon semiconductor layer and adjacent the substrate surface and the gate is provided on the other side of the semiconductor layer remote from the substrate surface. Examples of such a TFT used in an active matrix LCD are described in EP-B-0 179 914 and EP-B-0276340. In these devices, the source and drain electrodes are formed of ITO material from a deposited ITO layer which is used also to provide pixel electrodes and column lines for data signals, and an intrinsic amorphous silicon semiconductor layer formed by a PECVD (Plasma Enhanced Chemical Vapour Deposition) process extends between the source and drain electrodes to provide a channel region. Regions of the amorphous silicon semiconductor layer which extend over the source and drain electrodes may be doped (n+) to provide ohmic contacts.
One particular problem experienced with these kinds of TFTs is that it is difficult to make good quality contacts between the source and drain electrodes and the amorphous silicon layer reproducibly and hence uniformly. It is believed that when the amorphous silicon material is deposited by a PECVD process using a standard source gas composition having a hydrogen gas content, such as silane (SiH.sub.4) with H.sub.2, at a temperature of around 250.degree. C., as commonly used for amorphous silicon deposition, hydrogen reduction of the underlying ITO material can occur. Attempts to vary the source gas composition with the aim of reducing or avoiding this problem have tended to result in TFTs exhibiting poorer performance, particularly as regards stability and mobility, in subsequent use.
Another example of such a TFT is described in the paper entitled "An Ohmic Contact Formation Method for Fabricating .alpha.-Si TFTs on Large Size Substrates" by Yukawa et al published in Proceedings of the 9th International Display Research Conference, Oct. 16-18, 1989, Kyoto, Japan, Japan Display '89, at pages 506-509. The paper describes previous difficulties in making uniform low-resistance contacts for bottom drain and source electrodes to the silicon film of a top-gate TFT. These difficulties, it is said, had resulted in most flat panel displays being formed with bottom-gate TFTs, in spite of the many advantages of top-gate TFTs. The paper proposes avoiding these difficulties by doping the amorphous silicon semiconductor layer with phosphorus from the ITO source and drain electrode patterns. Thus, a film of ITO deposited on a substrate is etched to form a desired pattern of pixel electrodes and source and drain electrodes and tracks for the TFTs, and this ITO pattern is then exposed to an RF glow discharge of PH.sub.3 (phosphine). As a result, phosphorus dopant is adhered to the surface of the IT0 pattern. After an optional etching stage, an undoped hydrogenated amorphous silicon film is then deposited using a PECVD process to provide the channel region of the TFT. During this deposition, n+ regions are formed in the amorphous silicon film adjacent the ITO pattern by phosphorus diffusion from the surface of the ITO. This doping of the semiconductor film from the ITO source and drain electrodes is intended to give a good quality low resistance ohmic contact for the source and drain electrodes of the TFT. However, it has been found that although some improvement in the quality of the contacts between the source and drain electrodes and the amorphous silicon layer can result when using source gas compositions comprising SiH.sub.4 and H.sub.2 for the silicon layer deposition, similar undesirable interactions with the ITO, in the form of hydrogen reduction, can still occur so that any improvement is still limited. Moreover, the fabrication process entailed involves further processing steps which add to the complexity of manufacture.